1. Field of the Invention
Embodiments of the present invention generally relate to a method of ruthenium layer formation and, more particularly to methods of ruthenium layer formation for use in copper integration.
2. Description of the Related Art
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices. The multilevel interconnects that lie at the heart of this technology require the filling of contacts, vias, lines, and other features formed in high aspect ratio apertures. Reliable formation of these features is very important to the success of both VLSI and ULSI as well as to the continued effort to increase client density and quality on individual substrates and die.
As circuit densities increase, the widths of contacts, vias, lines and other features, as well as the dielectric materials between them may decrease to less than about 250 nm, whereas the thickness of the dielectric layers remains substantially constant with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many conventional deposition processes have difficulty filling structures where the aspect ratio exceeds 6:1, and particularly where the aspect ratio exceeds 10:1. As such, there is a great amount of ongoing effort being directed at the formation of void-free, nanometer-sized structures having aspect ratios wherein the ratio of feature height to feature width can be 6:1 or higher.
Additionally, as the feature widths decrease, the device current typically remains constant or increases, which results in an increased current density for such feature. Elemental aluminum and aluminum alloys have been the traditional metals used to form vias and lines in semiconductor devices because aluminum has a perceived low electrical resistivity, superior adhesion to most dielectric materials, ease of patterning, and the ability to obtain aluminum in a highly pure form. However, aluminum has a higher electrical resistivity than other more conductive metals such as copper. Aluminum can also suffer from electromigration leading to the formation of voids in the conductor.
Copper and copper alloys have lower resistivities than aluminum, as well as a significantly higher electromigration resistance compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Copper also has good thermal conductivity. Therefore, copper is becoming a choice metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.
A thin film of a noble metal such as, for example, palladium, platinum, cobalt, nickel and rhodium, among others may be used as an underlayer for the copper vias and lines. Such noble metals, which are resistant to corrosion and oxidation, may provide a smooth surface upon which a copper seed layer is subsequently deposited using for example, an electrochemical plating (ECP) process.
The noble metal is typically deposited using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. Unfortunately, noble metals deposited on high aspect ratio interconnect features using CVD and/or PVD processes generally have poor step coverage (e.g., deposition of a non-continuous material layer). The poor step coverage for the noble metal material layer may cause the subsequent copper seed layer deposition using an ECP process to be non-uniform.
Atomic layer deposition (ALD) processes generally provide high step coverage for deposition of transition metals, such as titanium, tungsten and tantalum, but has not been used as successfully for deposition of noble metals. For Ru-ALD processes, ruthenium layers have been deposited by using various ruthenocene compounds (ruthenium-containing metallocenes), such as bis(ethylcyclopentadienyl)ruthenium, bis(cyclopentadienyl)ruthenium and bis(pentamethylcyclopentadienyl)ruthenium. However, Ru-ALD processes using ruthenocene compounds generally require particular process conditions, such as hydroxylated (—OH) or electron-rich (e.g., metallic) surfaces and absorption temperatures above 400° C. Ruthenium-ALD processes with ruthenocene precursors generally deposit ruthenium layers having an increased electrical resistivity due to unevenness of the layer. Further, ruthenocene precursors used during Ru-ALD to deposit ruthenium on dielectric surfaces tend to fail the tape test due to low adhesion properties.
Therefore, a need exists in the art, for a method to deposit ruthenium metals in high aspect ratio interconnect features or dielectric surfaces having good step coverage, strong adhesion and low electrical resistivity.